Fully differential balanced output headphone amplifier
technical explanation

Copyright(C) 2022 Shoichi Yoshimoto

Internal photo

The chassis is open for explanation. Never open the chassis as there is a high voltage part inside.

Fully differential amplifier

Model10 uses a fully differential circuit to obtain high-quality balanced and unbalanced outputs at the same time.
A fully differential amplifier is an amplifier that has 5 terminals: + IN and -IN input terminals, + OUT and -OUT output terminals, and Vcom terminal.
The difference between + IN and -IN is amplified and output between + OUT and -OUT.
Vcom sets the midpoint voltage between + OUT and -OUT.
For headphone amplifiers, Vcom is 0V (ground).
Vcom keeps + OUT and -OUT at 0V when no signal is input (low DC offset).
At the time of signal input, a balanced voltage is output to + OUT and -OUT.

Fully differential amplifier structure

One channel of Model10 consists of 4 differential amplification stages and 2 SEPP output output stages.

'1' is a first-stage differential amplifier with 2N7002DW dual MOSFET.
The input signal is differentially amplified and sent to the positive driver stage '3' and the negative driver stage '2'.
'2' and '3' are driver stage differential amplifiers with NSS40300MDR2G dual PNP Tr.
Positive and negative signals are amplified to a large amplitude and sent to the SEPP stage by dual Tr.
Headphones are driven with low impedance by the SEPP stage.
'4' is a common mode feedback differential amplifier by NSS40301MDR2G dual NPN Tr.
Compare Vcom with the output midpoint and create an error signal to maintain the output potential and the balance between the outputs . The error signal is sent to the negative input of the driver stage and cancels the error (common mode) that occurs in the output.

Fully differential amplifier circuit

The figure below is a circuit diagram for one channel of Model10.

  1. The input signal is amplified by the U101 2N7002DW dual MOSFET differential amplifier.
    The positive phase output is sent to the positive phase driver stage of the Q102 NSS40300MDR2G dual PNP Tr.
    The negative phase output is sent to the negative phase driver stage of the Q103 NSS40300MDR2G dual PNP Tr.
    Since the dual element has good thermal coupling, the voltage fluctuation of the output can be reduced.
  2. The positive and negative phase driver stages create the + -8VP-P drive signal required for 3.5W output.
    The driver stage is a differential amplifier, but it operates as a grounded emitter amplifier for signals.
  3. Two diode-connected dual Trs and a 22 ohms resistor on the collector side of the driver stage create the bias voltage for the SEPP output stage.
  4. The SEPP output stage consists of dual Trs. Since the output Tr and the diode-connected Tr for bias are closely thermally coupled, the bias current is kept stable.
    The SEPP output stage consists of NSS40301MDR2G dual NPNTr and NSS40300MDR2G dual PNPTr. The NSS40301MDR2G and NSS40300MDR2G are high-performance Trs with a maximum collector current of 6A and hfe of 400. It drives 32 ohms headphones sufficiently.
    The idling current of the SEPP output stage is 14mA.
  5. The positive phase SEPP output and the negative phase SEPP output are connected by two 300 ohms resistors (R120, R121).
    If the positive and negative outputs are perfectly balanced, no signal will appear at the coupling point of the two 300 ohms resistors (R120, R121).
    The unbalanced component (common mode component) of the output appears here.
  6. The unbalanced component (common mode component) is compared with Vcom by the differential amplifier of Q104 NSS40301MDR2G dual NPNTr.
    In Model10, Vcom is 0V. The difference between the unbalanced component (common mode component) and 0V is returned to the positive-phase and negative-phase driver stages as an common mode feedback signal.
  7. An common mode feedback is created from the coupling point of the 300 ohms resistor (R120, R121) to the Q104 differential amplifier, and to the positive and negative phase driver stages.
    As a result, the unbalanced component of the output signal is canceled and the output potential when there is no signal is maintained at Vcom (0V).

About dual elements

Model10 uses dual elements in all stages.

  1. 2N7002DW
    The 2N7002DW used for first-stage differential amplification is an Nch dual MOSFET for small signals.
    Contains two Nch MOSFETs for small signals with the same characteristics.
    MOSFETs are often used for power applications such as output stages, but they are also useful for the first stage.
    MOSFETs for small signals have the following advantages over junction FETs.
    2N7002DW Data Sheet
  2. NSS40301MDR2G dual NPNTr and NSS40300MDR2G dual PNPTr
    It is called Dual Matched Transistor, and contains two Transistors with hfe difference within 10% and Vbe difference within 2 mV.
    The maximum collector current is 6A and hfe is 400 class in a wide range from 1mA to 1A.
    Due to its high performance, it can be used for various purposes from small signal voltage amplification to SEPP output stage.
    Model10 uses this dual Tr for all amplification stages except the first stage differential amplification.
    NSS40301MDR2G Data Sheet
    NSS40300MDR2G Data Sheet

No adjustment, highly stable SEPP output stage

Since Model10 is a balanced output with a stereo configuration, it has four SEPP output stages.
The idling currents of the four SEPP output stages must be set and maintained the same.
In order to improve productivity and reliability, the idling current of the SEPP output stage has been noadjusted and stabilized.

The left of the figure below is the general SEPP output stage, and the right of the figure below is the SEPP output stage of Model10 using dual Tr.
In a general SEPP output stage, it is necessary to adjust Rb as a variable resistor or select a temperature compensation diode in order to achieve the target idling current value.

Model10 gained the following advantages by replacing the temperature compensation diode with a dual Tr diode connection.
@EPerfect temperature compensation with adjacent diodes and Trs in the same silicon chip.
@ESince the diode and Tr have the same process and the same manufacturing conditions, the Vbe characteristics are the same.
As a result, the target idling current value can be stably obtained even if Rb is used as a fixed resistor.

The figure below shows the idling current measurement results from the time the power is turned on until 30 minutes have passed.
Immediately after the power is turned on, the idling current is 15mA, but after 5 minutes it stabilizes at 13.5mA.

Protection circuit

Since Model10 is a DC amplifier, a protection circuit is provided to protect the headphones from the following events.

Headphones are more vulnerable than speakers, so highly sensitive DC output detection is required.
Furthermore, since Model10 is a balanced output stereo amplifier, it is necessary to detect DC output at four points.
The protection circuit operates the relay under the following conditions to disconnect the headphones.

If these protection operations are realized by a conventional circuit, it will be large-scale.
Therefore, it is realized simply by using the PIC microcomputer PIC16F1823.
PIC16F1823 is a microcomputer equipped with high functionality such as 7ch 10Bit AD input in a 14pin DIP package.

The 10Bit AD input monitors the headphone output for 4 channels and the voltage of the power supply.


Almost all circuits are mounted on one printed circuit board.

Circuit diagram

Below is a PDF file of the circuit diagram on the printed circuit board.
Model10 headphone amplifier board complete circuit diagram (.pdf)

Characteristic list

Balanced output Unbalanced output
Output power 3.5W/32ohms 1W/32ohms
Gain 14dB 7B
Frequency Response DC - 250kHz (-3dB)
Distortion at 100 mW@ 0.01% or less 0.01% or less
NoiseiUncorrectedj 48uV 29uV
NoiseiHearing correctedj 34uV 17uV

Frequency Response

Balanced output

Unbalanced output


Balanced output

Unbalanced output

10KHz square wave response

Balanced output 10KHz square wave response
The upper line is the input waveform and the lower line is the output waveform. Click to enlarge.

32 ohms load 32 ohms +0.001uF 32 ohms +0.01uF 32 ohms +0.1uF

Unbalanced output 10KHz square wave response
The upper line is the input waveform and the lower line is the output waveform. Click to enlarge.

32 ohms load 32 ohms +0.001uF 32 ohms +0.01uF 32 ohms +0.1uF

Output offset voltage

Since Model10 is a DC amplifier, the offset voltage generated at the output must be suppressed.
A low offset voltage is realized by adopting dual elements for all amplification stages and fixing 0V by common mode feedback.

The figure below shows the offset voltage measurement results from power-on to 30 minutes.